Hybrid Memory: Altering the Target Market Changes the Value Proposition
Hybrid Memory: Altering the Target Market Changes the Value Proposition
By Bob Merritt and Sherry Garber, Convergent Semiconductors
In an industry that has spent billions to offer smaller, faster and cheaper devices based on an underlying theory that the industry-wide value proposition would be best served by doubling the number of transistors per silicon area at a constant rate, the shift toward a consumer-oriented market based on mobile devices is forcing a reassessment of this approach. As process nodes shrink and manufacturing complexity increases, and the semiconductor industry is once again attempting to fund impending large capital investments in a mature market burdened by commodity pricing, an increasing number of current projects point to the integration of application-focused performance attributes as being the major target application that will support the next generation of new technologies.
Intel CEO Paul Otellini said at the keynote presentation for the Intel Developer Forum in September 2009, "I can easily see a time where Intel will ship more SoCs than standard microprocessors." A statement from TI’s OMAP platform marketing manager in a recent interview with Chip Design magazine also captured the technology and manufacturing challenges resulting from this shift in technology emphasis: “When you have a chip that includes wireless, LAN connectivity, Bluetooth and GPS, all of those technologies have to be integrated with each other. Through-silicon vias are one approach we are looking at. There also has to be more integration at the package level.”
In Cadence’s recent vision paper EDA360, on the complexity of future SoC designs, the company points out that, “Today, systems and semiconductor companies are undergoing a disruptive transformation so profound that even the best-known companies will be impacted… The disruptive transformation we are speaking of is not about EDA developing new design tools. It is not about new methodologies. It is not about the functional verification crisis, or the move to electronic system level (ESL) design, or any of the issues that have dominated discussions about EDA to date. It is about something much larger. It begins with a shift from design creation to integration in the electronic systems industry, and results in a new focus on profitability.” Cadence paper: http://www.cadence.com/eda360/Pages/default.aspx?CMP=100427eda360_sb
We completely support that scenario. Within that context, we anticipate an emerging new class of devices that incorporate memory technologies combined at a higher level of integration into a single IC device along with logic or analog circuitry. This device can be used as a standalone memory device such as today’s NAND solid-state disk drives, or with all the enhanced digital/analog features the additional logic can bring to bear, as exemplified by Ramtron’s MaxArias Secure Wireless FRAM Memory, in which the memory array is powered by energy harvested from RF reception. The ability of these new devices to continue to act as a unique device by way of common interfaces defines its hybrid qualities and flexibility of features as well as enables rapid market acceptance.
We believe there will be an expanded set of these devices over the next decade that includes the performance attributes of memory, logic, and analog technologies. Basic memory technologies will be packaged with logic and analog features using the emerging advanced packaging technologies and eventually combined into a single die using a common fabrication process. The higher functionality and profitability from incorporating these capabilities into a single package will become a major enabler for emerging nonvolatile memory technologies that are more compatible with CMOS logic processes, and will result in significant displacement for those companies that have not embraced the significance of this capability.
The following chart identifies a targeted gross margin of 45 percent for Hybrid Memory companies extrapolated by Convergent Semiconductors that lies between the reported gross margins for selected memory and logic companies.
Targeted Gross Margin for Hybrid Memory
Source: Morningstar, Corporate Reports, and Convergent Semiconductors
Cadence’s vision paper further describes a future requirement for higher levels of integrations for more complex SoC designs that are partially brought about by the transitions in manufacturing strategies discussed above. Those same market conditions and EDA requirements are also eventually applicable to higher levels of performance and integration for multiple die in single packages. The value proposition for this end product is based on utilizing the flexibility of existing silicon while relying heavily on externally designed silicon and software IP, with an overall cost/performance ratio geared toward mature process nodes and embedded software development in order to achieve aggressive cost/performance advantages.
We believe that this conversion will occur over a period and will be accomplished in several phases, which are described below.
Phase 1 — Multi-Chip Package (MCP) Hybrid Memory
The essence of the packaging concept is to identify the functional boundary conditions at which the performance and the interface are optimized. Multi-Chip Packages (MCP) and Multi-Chip Modules (MCM) are already in general usage by memory companies and OEMs, hence the “Hybrid Memory” (HM) label we have applied to the technology trend. MCP is the packaging choice for smart phones. Products in high-volume production already range from pre-packaged ICs on small printed circuit boards meant to mimic the package footprint of an existing chip package all the way to fully-custom chip packages integrating many chip dies onto a single high-density substrate. Existing programs to improve the performance and lower the costs of TSV technologies, higher levels of design integration for EDA companies, and more sophisticated programs for predicting the performance of known good die (KGD) all improve the manufacturing efficiencies in this phase.
SiP Hybrid devices take advantage of the ability to combine memory die (or a memory plane) with digital logic circuitry (or digital layer). SiP incorporates a mix of components (logic, analog memory functions) into a single package. This stage is easily identified by heavy reliance on more complex TSV technology. These devices offer additional performance, flexibility, and time-to-market advantages compared to discrete semiconductor devices. Products based on technologies are already being implemented with high-performance thru-silicon-via technology used for vertically stacked memory dies in a single IC package, such as OneNAND and eMMC. This second phase will be implemented in the mobile consumer segment where the benefit is great from time-to-market advantages, and from the ability to assemble more complex product configurations.
The third phase, Partial Hybrid, begins to de-emphasize commodity memory products and supports more complex combinations of components, along with standardized interfaces like SPI or equally well-established parallel interfaces. This phase is outside the standard five-year forecast window for volume adoption. The distinguishing characteristic of this phase is the integration of some logic or analog functions into a common memory/logic process. One of the primary characteristics of many of the new and emerging non-volatile resistive memory technologies such as phase change memory, is the closer compatibility with standard CMOS logic processes. The maturity of those memory technologies should be developed to the point that they can become a factor at this level of production in applications with limited requirements for external memory. In terms of a time scale, this would also roughly correspond to the growing difficulties of supporting charge storage technologies would have become problematic due to the extremely small amount of material in the cell mass. This phase offers a lower risk and higher value opportunity to accelerate the production of new memory technologies. This ability to mix together within a single process features that have traditional required different processes will enable the ability to rapidly add new capabilities to existing digital products. This additive ability extends the current model of adding more memory to electronic devices over time. Consumer devices of the future will implement this phase to reduce BOM cost and increase feature variability.
Phase 4 — Full Hybrid Memory
The final transition phase, Full Hybrid, is driven by the ability to combine high-performance logic and high-performance nonvolatile memory within the same die. Full Hybrid Memory solutions will also drive new revenues for CAD suppliers and foundry equipment suppliers as a single process emerges for both memory and logic devices. For companies developing new memory technologies, this new market category promises to offer a faster means for new memories to enter the market, and provides the early market movers an opportunity to define and establish a dominant market share in a category we believe could rival the current global market for memory devices.
At this phase, we expect that the ability of EDA systems capable of supporting a level of integration combining more complex elements from different die would have achieved a similar level of importance as the ability to insert more transistors per silicon area.
Customers look forward to highly customized hardware and software solutions that are able to address the ultimate market of a single buyer. However, that goal seems to be in conflict with maintaining traditional cost/performance except for a limited number of very large IC manufacturers.
The ultimate motivation for the shift to Hybrid Memory will be the recognition by the memory companies, OEMs, and the end customer that a fundamental shift has occurred in how semiconductors can best adapt to end-market applications. Establishing hardware customization opportunities that follow software’s level of customization are essential in order to achieve this degree of product flexibility.
The entire spectrum of manufacturing will have opportunities to advance along with the four phases of HM. Of key importance to equipment manufacturers will be the extended demand for generations of processing equipment. While new technology and the equipment it requires will continue to be in demand, so will expanded capacity for established technology. Demand for a given generation of equipment will continue to be required for new or expanded fab capacity to produce the packaged hybrid memory of Phase 1 and 2 or the advanced use of technology of Phase 3 and 4.
New alliances are being formed, and new opportunities are unfolding at an accelerated pace as all semiconductor companies seek optimal realignment as the world’s economies recover. The commitment of major semiconductor companies to the development of new memory technologies makes headlines on a regular basis.
About the Company
Convergent Semiconductors and Edison Labs combine engineering expertise, semiconductor industry experience, logic and memory marketing insight, manufacturing infrastructure knowledge, and OEM design experience. These services offer the strategic analysis needed to understand the converging technology and application demand trends that will define investments and products for the decade.
A series of reports details this trend from concept to reality by presenting memory-enabled devices, the infrastructure to produce them, and the applications that will sustain new memory technologies. The reports also examine why so many of the new memory technology participants are outside of the recognized circle of high-volume memory manufacturers.
Additional information is available on our website: www.convergentsemiconductors.com
SEMI Global Update
June 1, 2010
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