SEMI EPWG Releases Report on Economics of 450 mm Wafer Transition
Many people in the industry seem to think that moving to larger wafers is the obvious next step to keep on Moore’s Law and to ensure that the cost per transistor continues to decline as it has in the past. It’s a reasonable assumption, since such a move is on the ITRS roadmap. But before making such a change – and before investing some tens of billions of dollars to make a change – it’s prudent to do a careful analysis of the facts and the myths around such a transition. SEMI’s Equipment Productivity Working Group (the EPWG) has done such an analysis.
Their conclusions are several.
The semiconductor business today – and for the foreseeable future – is consumer-driven, and needs to be capable of handling short-run, rapid-change products with very short cycle times to accommodate the lifecycle of the products now sold in the market.
The research and development dollars for shrinks, new processes, and new materials are highly constrained, and must be invested where they will offer a demonstrable positive return. Somewhat surprisingly, the change to a larger wafer size in itself does not lead to significantly reduced costs. Intel saw this in the changeover from 150 mm to 200 mm, and the same will be true for a change from 300 mm to 450 mm.
The true driver of the overall reduced cost for 300 mm wafers was the use of factory automation (that is, advanced materials handling systems, or AMHS), advanced process control systems (APC), mini-environments (FOUPs), and stopping work on 200 mm node advancement.
Shrinks, new materials, and new processes will continue to advance the industry on Moore’s Law, but there are simply not enough R&D resources available to continue such advancement in nodes and processes AND to work on a 450 mm wafer size transition.