Both pricing and technical pressures are a way of life within the entire semiconductor supply chain. The production test floor is no different. The European Manufacturing Test Conference (EMTC) will focus on key topics that have a strong impact on Operational Equipment Effectiveness (OEE), Time to Market, as well addressing the need to continue down the cost curve (COT).

As the ITRS International Technology Roadmap for Semiconductors (ITRS) outlines, integration levels are getting higher, devices are getting smaller, gate oxides are getting thinner, gate leakage is getting higher, and frequencies are getting higher. Roger Barth of Numonyx will address theses and other trends in the EMTC keynote speech, entitled “ITRS Test Roadmap Impacts On Manufacturing Test,” Roger Barth of Numonyx.

An innovative approach to reducing test cost is to create a more flexible test program. By monitoring test results over a certain period of time, one can then make intelligent decisions about the usefulness of the various tests that are being performed. While the term “adaptive test” has been around for years, the specific applications that use such techniques are just now rolling onto test floors — and these techniques are saving large amounts of money and time. Adaptive testing involves changing test strategies automatically, based on initial test results and established decision criteria, such as changing force/measure levels or changing the number of test sites. Adaptive test strategies can be implemented after process changes, a new fab or other scenarios.

At EMTC, Réne Segers, NXP Semiconductors, and Dan Glotter, Optimal Test will give a presentation, entitled, “Adaptive Test at NXP,” that will provide insights into the chip makers test strategies. The Adaptive Testing session will also include presentations by John Bearden from Optimal Test and Steve Ledford, Verigy.

Cost of test is directly related to cycle time and test program creation. Christian Bonnin, ATMEL Rousset, and Bob Whyte, Credence Systems Corp, will give a talk called, “TPG (Test Program Generator) – Generating a Full Test Program for a New Device in 1 Hour,” that will provide practical solution on cycle time. Cost Of Test (COT) will be the entire theme of Stephane Mougin, STMicroelectronics, presentation on “How to Keep Pace with the Current Test Challenges,” and a major element of Verigy’s presentation on “Parallel RF Wafer Sort Production Testing.”

New technologies are also critical to managing today’s test challenges. Laser Direct Testing, or LDT, is a process that consists of extracting electrons out of conductive pads (test points), but sink electrons into conductive pads as well, having an actual current flowing through traces allowing testing for Continuity and Isolation. Laurence Pujol, Beamind will discuss how LDT can be applied to IC package substrates.

Davide Appello, STMicroelectronics (chairman)

Martin Stadler, Teradyne (vice-chair)

Gary Sheedy, Advantest

Klaus-Detlef Paesch, AMD

Michael Goldbach, LTX

Peter Muhmenthaler, Infineon Technologies

René Segers, NXP Semiconductors

Robert Whyte, Credence

Ulrich Schoettmer, Verigy

Roger Barth, Numonyx

For more information on the EMTC and SEMICON Europa, visit http://www.semiconeuropa.org/ProgramsandEvents/TestandAdvancedPackaging/CTR_024174?parentId=144&parent=yes&linkval=Test Conference EMTC