Perhaps no other segment of the semiconductor industry has experienced more innovation in recent years as assembly and packaging. Many believe the transistor is no longer the limiting factor in cost or performance of an electronic product, and that assembly and packaging solutions will drive the industry. Supporting and enabling many of these innovations are new test methodologies, instrumentation and equipment. Technical and business leaders in test, assembly and packaging (TAP) from throughout the world will converge on SEMICON Singapore on May 2-5 to discuss the critical issues, innovations and opportunities in equipment and materials necessary to bring advanced chips to market in economical and productive forms.

In recent years, there has been strong adoption of chip scale packaging (CSP), stacked die packaging, and wafer-level (WLP) form factors to meet the needs in portable and electronic products. Flip chip applications also continue to grow. Packaging types will continue to expand as no single type meets the performance and form factor needs of the increasingly diverse set of consumer electronic products. Packaging material technology will also evolve to meet critical industry needs in electrical and thermal performance as well as process integration and system reliability (see SEMI article)

While innovation speeds forward, business conditions challenge equipment and materials suppliers. Gartner recently shocked the industry by forecasting the worldwide packaging and assembly equipment market to fall 18.1 percent in 2008. However, Gartner analysts indicate that recent data suggests the industry may have hit the bottom in the first quarter of 2008. Gartner also reports that the worldwide automated test equipment market declined 14 percent in 2007, and analysts expect a similar decline of approximately 13 percent in 2008, as test providers remain cautious with capital budgets. Gartner analysts expect improved market conditions beginning in the middle quarters this year.

While the overall TAP market is bleak, Southeast Asia market remains robust, especially the countries of Singapore, Malaysia, Indonesia, Thailand, and the Philippines. For 2008, Gartner forecasts another year of growth for the outsource test and assembly industry with initial estimates of 9.8 percent over 2007. Nearly all major outsourcing firms are expanding in the region, and last year the fastest growing test and assembly service provider was Singapore-based UTAC at 18.5 percent growth. This region is a leader in the market of assembly and test equipment and is the second largest market for packaging materials. In addition, new fab investments continue to make significant strides in the region.

It is estimated that capital spending will decline by 10% to 15% globally in 2008, but Southeast Asia is estimated to increase capex for the year (see SEMI article). For Southeast Asia, the semiconductor equipment market is expected to grow from $3.05 billion to $3.13 billion in 2008. The assembly and test equipment market represents about 50% of this market, given the strong presence of assembly and test plants in the region.

Scott Kulicke, chairman & CEO, Kulicke & Soffa, will provide his perspectives and insights on the TAP innovations and business challenges at SEMICON Singapore’s 8th annual Semiconductor Market Trends Briefing. Also providing the latest insights into market trends and opportunities at the Market Briefing will be Dan Tracy from SEMI, Jeremy Sim, SAS, and Jan Vardaman, TechSearch International, Inc. A presentation on the future of the disk drive industry will also be discussed by David Reinsel, VP, Storage and Semiconductor Research, IDC.

Kicking off the Semiconductor Technology Symposium (STS), Advanced Packaging Technologies session will be Ms Jean Ramos, Chief Technology Officer, Unisem, presenting “Lower Cost” Packaging Technologies: Exploring the Benefits of Copper Wire Bonding”. Also to be discussed at the Day 2 STS session will be new materials and approaches for wire bond and new approaches to die attach.

The Day 2 session will be highlighted by keynote speaker Mario Bolanos, Director, Semiconductor Packaging Technology Research at Texas Instruments, who will discuss “Main Drivers of New Packaging Technology Trends”. Other topics on Day 2 include 3D packaging and the future of TSV technology, wire bonding challenges for sensitive metallization, and SIP technology overviews.

The STS Program will also include a full-day on test technologies on Tuesday, May 6. Michael W. Schraeder, Vice President Test Products and Services at STATSChipPAC will present the keynote on, “Trends, Market Drivers and Outlook – IC Assembly and Test, 2008 and Beyond.” Additional presentations will be given by Infineon Technologies (semiconductor failure analysis), Verigy (parallel RF test), Chartered Semiconductor (efuse methodology and characterization), LTX (RF SoC test), and Everett Charles Technologies (probe designs).

For more information on SEMICON Singapore, visit www.semiconsingapore.org

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