8:15am–8:55am

Registration and coffee

Session 1: Small Problems – Big Solutions

Session Sponsor:

8:55am–9:30am

Keynote: Known Good Die in the Era of Deep Submicron and 3D Integration
Dr. Bill Bottoms, Chairman and CEO, Third Millennium Test Solutions,
ITRS Roadmap Committee Chairman

9:30am–9:55am

Junction Leakage Degradation
Chi-Li-Ma Harnold, Team Lead, Nanya Technology

9:55am–10:20am

Fine Pitch Copper Wire Bonding Implementation Down to Deep Submicron
Bernd Appelt, Director of Business Development, ASE Group

10:20am–10:40am

Break

10:40am–11:05am

Scalable Microspring Contacts for Integrated Test and Packaging
Eugene Chow, Principal Scientist, Palo Alto Research Center (PARC)

11:05am–11:30am

Development of a KGD LSI Chip Carrier with 10 Micron Sq. Contact Micro Bumps for Chip Level Burn-in Testing
Masahiro Aoyagi, Principal Research Scientist, National Institute of Advanced Industrial Science and Technology; M. Miura, STK Technology Co., Ltd.

11:30am–11:55pm

Chip Traceability with Inkjet Marking
Yoshio Nogami, Director, General Manager R&D Center, Toray Engineering

11:55am–1:15pm

Lunch

Session 2: Process Improvements

Session Sponsor:

1:15pm–1:40pm

Test Process Control: Real-Time, Automated Methods to Improve Yield and Lower Cost
Kevin McCarville, Pintail Technologies

1:40pm–2:05pm

Increasing Yield and Reducing Field Failures for Very Large Die & Very Small Die on Large Wafers Through the Application of Multiple-Flow Statistical Post Processing of Wafer Probe Data
Kate Cuccurello Rutz, Senior .Applications Engineer, Galaxy Semiconductor

2:05pm–2:30pm

Cost versus Reliability Tradeoffs for Stacked Devices
Steve Steps, Senior Director of Wafer Level Burn-in and Test, Aehr Test Systems

2:30pm–3:00pm

Break

3:00pm–3:25pm

Treating an Inspection Tool as a Metrology Tool—Achieving Zero Defect Inspection for Automotive Customers
Rajiv Roy, VP Business Development and Director, Back-end Marketing, Rudolph Technology Corporation

3:25pm–3:50pm

Characterization of Trenches and Vias with Model-Based Infrared Reflectometry
Leif Jonny Hoglund, Senior Applications Engineer, Semilab AMS

4:00pm–5:00pm

Panel Discussion: Is KGD Required for TSV?
Moderator: Jan Vardaman, TechSearch International, Inc.
Panelists:

Rajiv Roy, V.P. Business Development, Rudolph Technology Corporation
Dan Rishavy, Product Manager Test Systems, TEL
Mike Slessor, CEO, MicroProbe, Inc.
Michael Wright, General Manager, Cascade Microtech, Inc.
Bill Bottoms, Chairman and CEO, Third Millennium Test Solutions and ITRS Roadmap Committee Chairman

6:00pm–9:00pm

BBQ Dinner at the County Line
(bus transportation provided)

Sponsored by:

Session 3: KGD for Embedded Solutions

Session Sponsor:

8:30am-8:55am

KGD Cost Modeling for Embedded Products
Alan Palesko, SavanSys Solutions, LLC

8:55am–9:20am

Chip Embedding into PCB Substrates without KGD
Thomas Gottwald, Head of Product Engineering, Schweizer Electronic

9:20am–9:45am

KGD for Embedded Products
Georg Meyer-Berg, Infineon Technologies

9:45am–10:00am

Break

10:00am–10:30am

LED Test and Packaging Challenges: A User Perspective
Brad Bailey, VP of Engineering, FireFly LED Lighting, Inc.

Session 4: Wafer Sort and Handling Improvements

Session Sponsor:

10:30am–10:55am

Wafer Sort Methods Employed to Achieve Automotive Customer’s Zero ppm Requirements
Robert Doherty, Wafer Sort Process Engineering Manager, Analog Devices

10:55am–11:20am

New Advancements in Ultra-thin Die Handling and Flip Chip Inspection
Gerald Steinwasser, General Manager Muhlbauer, Inc

11:20am–11:45am

Tape and Reel Packaging System for Finer Bare Die Geometries
James Adams, Applications Engineer Specialist, 3M

11:45pm–12:10pm

Practical Considerations for RF Wafer Sort Testing in Production
Swee Heng Goh, STATS ChipPAC

12:10pm–1:10pm

Lunch