Lithography TechXPOT: Looking at the End of the Line for 193

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Lithography TechXPOT: Looking at the End of the Line for 193

The life of 193 nm lithography has been extended many times; advances in OPC, water immersion, and double-patterning have allowed the semiconductor industry to use this technology down to the 32 nanometer node. However, the wavelength physics of this light source can only be stretched so far, and new solutions must be in R&D now in order to be available for high-volume manufacturing (HVM) in the next few years.

The SEMICON West 2009 Lithography TechXPOT brought together seven experts from across the industry to assess where we are today, how long we can keep going, and what new approaches are in the development phase. Whether these solutions will be implemented, and when, will determine the pace of technology advancement in semiconductor manufacturing, and these experts brought their perspectives to the discussion for a “standing-room only” audience. These are the highlights from the presentations, which are posted on the website at: Scaling&parent=yes&parentId=5

Lithography 2009: Overview of Opportunities, by Yan Borodovsky, Intel senior fellow, Technology and Manufacturing Group, and director, Advanced Lithography, Intel Corporation

Dr. Borodovsky started with the observation that Intel will be entering HVM at the 32 nm node with single-exposure 193i technology by the 4th quarter of 2009. After that, though, the 22 nm node will be the last opportunity for such technology, and getting down to the 15 nm node will require use of pitch division. The roadmap for the 11 nm and 7 nm nodes will require some other solution, and Intel has EUV, maskless, and imprint under investigation as possible solutions. A significant choice will, according to Borodovsky, have to be made when EUV (appropriate for logic) and nanoimprint (appropriate for memory) are the two choices; the industry will likely not be able to fund development and implementation (much less support) of both approaches. Borodovsky’s likeliest scenario for the future will involve the use of 193i with pitch division for most of the production for logic and memory, supplanted with EUV for high-density critical features. The challenge will be to have an EUV solution ready by 2011 for HVM in 2013.

Nanoimprint: Affordable 22nm Lithography Now?, by Ben Enyon, vice president, Semiconductor Business Development, Molecular Imprints, Inc.

Mr. Enyon started with an observation made by Dr. Borodovsky – that logic and memory have different lithography requirements – and showed that nanoimprint technology would be a viable contender for both of these technology demands. Using nanoimprint to spray precise droplets of resist at exact locations, he said, is following the same defect improvement path as 193i did, but about two years later. This would put nanoimprint technology one course to support and eventually replace optical beam litho in the time frame needed for HVM at small nodes. The big concert remaining is mask replication, as these masks do not have the lifetimes seen and expected as those in use with 193i. Development work being done now with Dai Nippon Printing is expected to be available for commercial use by mid-2010, which would allow for HVM in the 2011 timeframe.

Advanced Imaging Solutions for Shrinking the k1 Gap, by Dr. Stephen Renwick, principal engineer, Nikon Precision

There’s still room in 193i for improvement, according to Steve Renwick of Nikon, and ArF will be stretched to cover the needs of upcoming nodes. The reduction in k1 is the best place to start, and Dr. Renwick illustrated the Nikon approach of having a “scanner file” that contains information specific to the scanner model being integrated into the mask design steps, thus using the best features of the tool model to increase CD uniformity and accuracy. The next step is to have such a file per individual scanner machine, thus taking the level of specificity up to the machine and allowing for optimization per scanner. This source and mask optimization can be combined with additional tuning using infrared sources to create mask that will allow for 193i to support nodes for the foreseeable near term, according to Renwick. After that, it will be EUV, and starting the industry-wide learning and optimization curve all over again.

Double Patterning, by Matt Colburn, manager, Advanced Lithography IBM

Mr. Colburn explained in detail the use of double-patterning to create features smaller than the wavelength of the light source. The development of this approach has given us the double-exposure, double-etch approach and the double-exposure, single-etch approach, each with strengths and weaknesses. The “Pitch-Split Double Exposure” approach, where multiple exposures are combined, offers much promise but requires extremely tight overlay control; this is a reasonable approach for the short term. Colburn also noted that the drop in defectivity for these double-patterning and double-resist systems must exceed the drop for single-patterning systems, because the extra process steps are already a process throughput inhibitor.

Metrology Challenges, by Venkat Nagaswami, director, Patterning Technology, KLA-Tencor

Measuring the patterns created by double-patterning systems, and checking the uniformity of those patterns, is going to be difficult. The innovative process technology and new generation lithography techniques described offer considerable metrology challenges for the industry.

Double-patterning lithography creates CD uniformity and overlay issues, and not just in two dimensions. Wafer flatness and warping become even more critical with such small feature sizes. But, according to Ragaswami, required CD and overlay budgets can be achieved with carefully controlled parameters; among these are wafer flatness and wafer shape, mask pattern placement error, in-die metrology, and high-order overlay sampling. Solutions do exist today, but they are not inexpensive.

EUV Lithography: Ready for Manufacturing? By Bruno La Fontaine, fellow, Lithography, GLOBALFOUNDRIES

Is EUV ready for HVM? Dr. La Fontaine answered that question simply – No.

After going through an in-depth examination of the major issues around EUV, Dr. La Fontaine offered the conclusion that EUV lithography is a strong candidate for high-volume CMOS manufacturing. In pilot line and lab environments, the capabilities of EUV lithography have been well-established. The basic integration of EUV into a semiconductor manufacturing fabrication flow has been established. And fortunately, the initial cost targets for throughput, scanner price and mask price are within reach. However, “Timing is everything,” and the industry needs pilot line tools ready before 2012 to begin the learning and optimization necessary for HVM. In conclusion, said Dr. La Fontaine, the earliest possible insertion for high-volume production ramp is around the 2013 to 2014 timeframe – just slightly later than the industry expects it today.

EUV Readiness: An Infrastructure-Based Perspective, by Bryan Rice, director, Lithography, SEMATECH / Intel

After extensive industry analysis, the inescapable conclusion is that EUV’s key infrastructure gaps are in the area of mask metrology. Dr. Bryan Rice of Intel, on loan to SEMATECH, explained SEMATECH’s EUV mask infrastructure strategy. The plan is to commit most of SEMATECH’s lithography budget to mask infrastructure over the next four years, to obtain support from various partners (public and private) to continue research and development, and to coordinate the industry’s efforts to meet the critical needs for both EUV pilot line readiness (bridge tools) in 2011 and production (commercial tools) in 2013.

August 3, 2009