ASMC 2009

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Monday, May 11

Tuesday, May 12

Wednesday, May 13

ASMC 2009 Agenda

Registration & Hotel Information



Boosting manufacturing productivity has become a joint effort between device makers, equipment and materials suppliers and academics. These groups will display their collective manufacturing expertise at the 20th Annual IEEE/SEMI Advanced Manufacturing Conference—the industry’s longest-running global semiconductor technical conference. Join them in Berlin to network, learn and share expertise on the latest semiconductor manufacturing practices and concepts.

This year, ASMC features a special session presented by the International Symposium on Semiconductor Manufacturing (ISSM). Best paper awardees from ISSM 2008, held in Tokyo, will present on: AEC/APC, Advanced Lithography; Environment, Safety and Health; Manufacturing Control and Execution: Process and Equipment Control: Process and Materials Optimization: and Yield Enhancement Methodology.

The ASMC Agenda was created by a committee of more than 50 technical experts from Europe, North America and Asia. It features more than 75 peer-reviewed papers and keynotes from these companies and more:

  • Altis Semiconductor
  • AMD
  • Applied Materials
  • Chartered Semiconductor
  • DuPont
  • Fujitsu
  • Fraunhofer Institute
  • Hitachi High Technologies
  • IBM
  • Infineon
  • Intel
  • Jenoptik
  • KLA-Tencor
  • Linde Electronics
  • Nikon Precision
  • Qualcomm
  • Qimonda
  • Rexchip Electronics
  • Samsung
  • STMicroelectronics
  • Toshiba
  • Verrigy

Who Should Attend ASMC?

Plus, Semiconductor Professionals Involved in:

  • Chief Technology Officers
  • Fab Managers
  • Process and Yield Engineers
  • Line Supervisors
  • Product Managers
  • Technical Experts
  • Advanced Metrology
  • Advanced Process Control
  • Advanced Equipment and Materials Processes
  • Contamination Free Manufacturing (CFM)
  • Cost Reduction








Welcome to the Conference and ASMC Best Paper Presentations

Keynote: Light the Future—Innovation and Production at OSRAM Opto Semiconductors
Elke Eckstein,
COO, OSRAM Opto Semiconductors

Session 1: Defect Inspection I

Session 2: Advanced Equipment Processes and Materials I


  • Jeff Barnum, KLA-Tencor
  • Dieter Rathei, DR YIELD Software & Solutions
  • Kenneth Ye, Hitachi High Technologies

This session explores advances in techniques to address increasing challenges with in-line defect inspection, binning and analysis. Key topics include optical inspection utilizing design attributes for area selection and intelligent binning for defect pareto optimization as well as surface and edge inspection and characterization methodologies.


1.1 Opening Paper: Reduction of Defects Caused by Chemical Mechanical Polishing of Oxide Surfaces and Contamination of the Wafer Bevel— Stefan M. Gallus, Franz Niedermeier, Marco Maue, Infineon Technologies

1.2 Tracking of Design Defects Hidden in the Random Defectivity in a Production Environment J.C. LeDenmat, V. Charbois, M.C. Luche, G. Kerrien, STMicroelectronics; L. Couturier, L. Karsenti, Applied Materials France; M. Geshel, Applied Materials Israel

1.3 Novel Method to Generate Inspection Care Area Using GDS HoSung Kang, MinHo Kim, KiHo Kim, SooCheol Lee, JungA Choi, Samsung Electronics; YeonHo Pae, ChangHo Lee, Chris Lee, KLA-Tencor

1.4 A System to Optimize Inline Defect Detection Using Short Loop Testchips Leading to Faster Yield Learning T. Yang, H.C. Lee, V. Lim, F.H Gn, T. Mardiyono, Q. Wang, L. Nguyen, Chartered Semiconductor Manufacturing; Mark Spinelli, F. Li, S. Zhao, A. Inani, PDF Solutions



  • Alfred Koenig, Applied Materials
  • Jacek Tyminski, Nikon Precision

Advanced processes pose challenges both in the front-end and back-end of IC manufacturing. The session presents a range of solutions and reviews the impact on IC performance.


2.1 Opening Paper: Electro-Static Induced Metal Breakdown at Interlayer Dielectric Post CMP Brush Clean Process— S. Lariviere, F. Picoré, P.L. Saez, J.-L. Baltzinger, B. Delahaye, J. Matha, X. Gilhard, S. D’Oliveira, J.-M. Lagarde, J.L. Prebot, F. Merlot, F. Nogueira, Altis Semiconductor

2.2 Minimum Power Fail in High-Density Structure Improved by Chemical and Mechanical Polishing Optimization— L. Denis, V. Dureuil, C. Fournier, G. Richou, F. Nogueira, D. Petit, M. Bostelmann,
M. Comas, D. Dorval, P. Deconinck, B. Delahaye, Altis Semiconductor

2.3 TLS-Dicing—An Innovative Alternative to Known Technologies Hans-Ulrich Zuehlke, Gabriele Eberhardt, Patrick Mende, Jenoptik Automatisierungstechnik GmbH

2.4 Importance of Immersion Lithography Material Screening/ Optimization & Scanner Flexibility— Hamid R. Khorram, Nikon Precision Inc.; Katsushi Nakano, Natsuko Sagawa, Y. Ishii, Tomoharu Fujiwara, Yasuhiro Iriuchijima, Nikon


Conference schedule subject to change.



Session 3: Defect Inspection II

Session 4: Cost Effectiveness and Manufacturing Efficiency


  • Kazunori Nemoto, Hitachi High Technologies
  • Oliver Patterson, IBM

This session explores advances in techniques to address increasing challenges with in-line defect inspection, binning and analysis. Key topics include optical inspection utilizing design attributes for area selection and intelligent binning for defect pareto optimization as well as surface and edge inspection and characterization methodologies.


3.1 Opening Paper: Optimizing a 32 nm Development Fab’s HOL Defect Pareto Using iDO and eADC— Carol A. Boye, IBM; Sumanth Kini, Nithin Yathapu, KLA-Tencor

3.2 Quantifying Yield Impact of Polished Induced Defects on the Silicon Surface— Byeong Sam Moon, J.H. An, S.K. Park, N.J. Kwak, S.H. Lee, Hynix Semiconductor; Hideo Ohta, T. Watanabe, K. Ichinose, K. Nemoto, Hitachi High-Technologies

3.3 Identify Yield Loss in the Outer Dies Using SEM-Based Wafer Bevel Review— Britta Becker, Hanan Eschwege, Applied Materials; Heiko Freund, Qimonda

3.4 Improving Quality of Defect Pareto by Review Sample Shaping Using Defect and Design Attributes— Andrew Stamper, IBM Microelectronics; Barry Saville, Alexa Perry, Malcolm McLean, KLA-Tencor


  • Dave Gross, Advanced Micro Devices
  • Scott Lantz, Intel
  • Holly Magoon, Nikon Precision

IC supplies and their partners discuss innovative approaches to reduce costs and enhance productivity via fab forecasting, materials usage and employee wellness programs.


4.1 Opening Paper: Continuous Improvement Program: An ISMI Perspective— Tony Speranza, Phil Seidel, Harvey Wohlwend, Dale Wilt, Jo Beekman, Frank Nappi, Lorn Christal, Eric Greiger, Mike Schwartz, ISMI

4.2 Overcoming New Cu CMP Slurry Implementation Challenges through Slurry Pot Life Management— Carlo Dominic Aparece, Govindarajulu Venugopal, Wai Lwin, Jimmy Lo, Phua Yoke Hor, Chartered Semiconductor Manufacturing

4.3 Managing the Challenges of Multi-Product Manufacturing—Charles Weber, Portland State University; Asser Fayed, Cypress Semiconductor

4.4 Technology-Enabled Employee Wellness: Emerging Trends, Applications, and Results— Scott Lantz, Troy Severson, Intel


Session 5: Lithography Advances and DFM

Session 6: Factory Automation and Dynamics/Industrial Engineering

Chairs: Christopher Hess, PDF Solutions
Jennifer Braggin,

CD control of the poly layer is a key area driving new developments in advanced process technology nodes. The session will provide an overview of available litho enhancements and design layout features implemented to best complement today’s litho capabilities.


5.1 Opening Paper: Design-for-Manufacturing Features in Nanometer Processes—A Reverse Engineering Perspective— Dick James, Chipworks

5.2 Automated Vendor-to-Vendor Scanner OPE Matching

Stephen P. Renwick, Nikon Precision, Inc.

5.3 Poly-Width-Modification Method for Canceling
Layout-Dependent Characteristic Variations for
Low-Standby-Power CMOS Technologies

Satoshi Nakai, Kazushi Fujita, Takayoshi Minami, Junichi Mitani, Toshio Sawano, Masato Suga, Tatsuo Chijimatsu, Tatsuya Deguchi, Satoru Asai, Fujitsu Microelectronics

5.4 Etch Adjustment for Independent CD Control in Double Patterning— Sébastien Barnola, Céline Lapeyre, Isabelle Servin, CEA-LETI; Martin McCallum, Vincent Salvetat, Holly Magoon, Nikon Precision

Chairs: John Goodman, Entegris
Dave Gross
, Advanced Micro Devices
Peter van der Meulen,
BlueShift Technologies

Planning, scheduling and dispatching in fabs are critical to productivity and efficiency. This session showcases work that improves fab efficiency and cycle time, including simulation-based modeling to increase understanding of fab operations.


6.1 Opening Paper: Manufacturing Optimization Improvements Leveraging the E94-1107 SEMI Standard—Carmen Maxim, Raymond Goss, Michael Drozda, Diwas Adhikari, Advanced Micro Devices

6.2 Advanced Effective Dispatching Method for 300 mm Twin-Phase Twin-Fab— Cheng-Cheng Chang, His-Lo Lo, Cheng-Chung Pan, De-Lung Wu, Rexchip Electronics

6.3 Predicting Mean Cycle Time as Function of Throughput and Product Mix for Cluster Tool Workstations Using EPT-based Aggregate Modeling (student paper)—C.P.L. Veeger, L.F.P. Etman, J.E. Rooda, Eindhoven University of Technology; J. van Herk, NXP Semiconductors

6.4 First Wafer Delay and Setup: How to Measure, Define and Improve First Wafer Delays and Setup Times in Semiconductor Fabs— Stefan Radloff, Mario Abravanel, Dylan Steeg, Intel; Peter van der Meulen, Martin Petraitis, BlueShift Technologies


Interactive Session 7 and Reception (sponsored by KLA-Tencor)

Chairs: Thomas Beeg, Qimonda; Eric Eisenbraun, University at Albany; Franz-Josef Kahlen, University of Capretown; Winfried Meier, Nikon Precision Europe; Larry Pulvirent, Freescale; Theresa Roeder, San Francisco State University; Helmuth Treichel, Xyratex


7.1 40% Cycle Time Improvement as a Result of Continuous Improvement Activities— Bernd Janke, Uwe Kuschereitz, Qimonda Dresden

7.2 Design and Simulation of a Novel Nano Structure Quantum Well Voltage Regulator to Having a Low Regulated Voltage— Pejman Shabani, Shahid Chamran University; Jabbar Ganji, Islamic Azad University of Mahshahr

7.3 Design of Integrated 2x4 Decoder Based on the Quantum Well MODFET to Reduce the Scale of the IC— Pejman Shabani, Shahid Chamran University

7.4 Detection of Critical Defects with E-Beam Technology for Development and Monitoring of Advanced NAND Process— Hiroyuki Hayashi, Masafumi Oomura, Naoki Ihata, Toshiba; Akihiro Shinkawa, Frank Fan, Jufeng Li, KLA-Tencor

7.5 Development of a TiN-CVD Process with Very High Step Coverage— Guenther Ruhl, Michael Krenzer, Joerg-Martin Batke, Infineon Technologies

7.6 The dEWMA Fault Tolerant Approach for Mixed Product Run-to-Run Control — Ying Zheng, Bing Ai, Yanwei Wang, Hong Zhang, Huazhong University of Science and Technology

7.7 Edge and Extreme Edge-2mm Edge Exclusion- Process for Manufacturing in 200 mm Wafer Fab: Methodology, Yield Challenges, Cost Effective Solutions and Limitations— Bruno Delahaye, JL. Baltzinger, L. Denis, S. Chantepie, P. Costaganna, G. Richou, S. Lariviere, F. Aonzo, S. Delabriere, F. Poli, C. Bru, J.B.Meyniel, F. Allais, V. Dureuil, P. Raffin, E. Rondey, AltisSemiconductor

7.8 Factory Operational Curve—Logarithm Curve—Sylvain Bouhnik, Numonyx

7.9 Fully Automated Multi-Sensor Metrology for Front-end Use in MEMS and Semiconductor— Thomas Fries, FRT GmbH

7.10 Identifying Key Process Characteristics and Predicting Etch Rate from High-Dimension Datasets— E. Ragnoli, S. McLoone, J. Ringwood, NUI. Maynooth; N. Macgearailt, Dublin City University

7.11 Inline Defect Detection, Review and Characterization: Status and Challenges for 32nm Half-pitch Technology— Dilip Patel, Aaron Cordes, Milt Godwin, Chris Deeb, Doron Arazi, Kye-Weon Kim, Mark Johnson, International SEMATECH Manufacturing Initiative (ISMI)

7.12 An Iterative Outlier Screening Procedure for Reliability Data Using Mixed Effect Modeling— Sankaran Kartik Jayanarayanan, Helen Hu, Karen McGaughey, Advanced Micro Devices

7.13 Low-k Wafer Scribing Using Water Jet-Guided Laser Technology with 10 ns Lasers— A. Pauchard, S. Obi, B. Richerzhagen, Synova

7.14 Optimizing Flexibility and Equipment Utilization through Qualification Management— Carl Johnzén, Stéphane Dauzère-Pérès, Claude Yugma, Ecole des Mines de Saint-Etienne; Philippe Vialletelle, STMicroelectronics

7.15 Prediction of Chemical Consumption in Semiconductor Fabrication— Horst Zisgen, Hans-Jürgen Eickelmann, Manfred Haubrich, Frank Marschollek, IBM Deutschland; Richard Kleinhenz, IBM Microelectronics

7.16 Proof of Concepts: Virtual Metrology vs. Model-based Chamber Matching for Plasma Processing—M. Klick, L. Eichhorn, R. Rothe, Plasmetrex

7.17 Role of New Materials in Enhancing Productivity of Semiconductor Manufacturing Equipment— G. John Foggiato, Greene Tweed

7.18 Remote Cold Dry Etching: Manufacturing Processes in Pre-Assembly for Ultra-Thin Chips— Peter Heinze, PVA TePla AG

7.19 Superior Etch Performance of Ar/N2/F2 for CVD/ALD Chamber Clean— Marcello Riva, Solvay Fluor; Robert Wieland, IZM Fraunhofer Institute

7.20 Supervised Learning Methods in Sort Yield Modeling— Helen Hu, Advanced Micro Devices

7.21 A Systematic Methodology for Yield Excursion Handling— Using Semiconductor Wafer Foundry as a Case Study— Xiao-Qing Xu, United Microelectronics

7.22 Using Ebeam Inspection Tool for BF Inspection Tool Baseline— Randall Pak, Qimonda; Roland Hahn, KLA-Tencor

7.23 Yield Enhancement and Excursions Prevention Using Fault Detection and Classification Methods and Product Test Data— Hélène Ansquer, Christophe Balsan, Nathanaël Moreaud, Dominique Deprost, Altis Semiconductor

Conference schedule subject to change.


ASMC 2008 - ISMI Best Student Paper
Optimizing the Operating Curve: How Can Every Fab Maximize its Performance?
—Asser Fayed, Cypress Semiconductor and Charles M. Weber, Portland State University-ETM
ASMC 2008 Entgris Best Paper Award

Utilizing Design Layout Information to Improve Efficiency of SEM Defect Review Sampling
—Scott Jansen, IBM Microelectronic; Glenn Florence, Alexa Perry, KLA-Tencor




Registration and Welcome

Keynote: Semiconductor Manufacturing Outlook
Klaus-Dieter Rinnen,
managing vice president, Gartner-Dataquest

Session 8: Virtual Metrology

Session 9: Contamination Free Manufacturing (CFM)


  • Dick James, Chipworks
  • Graham McFarlane, Linde Electronics

Taking advantage of process tool sensors, virtual metrology offers a fast, cost effective complement to traditional in-line metrology. This session discusses front-end of the implementation of virtual metrology.


8.1 Opening Paper: Model Structure Improvement for Virtual Metrology in Plasma Etch— S. Lynn, J. Ringwood, E. Ragnoli, S. McLoone, NUI Maynooth; N. Macgearail, Dublin City University

8.2 Virtual Metrology Models for Predicting Physical Measurement in Semiconductor Manufacturing— Ariane Ferreira, Agnès Roussy, Lamine Conde, Ecole Nationale Supérieure des Mines de Saint-Étienne

8.3 SACVD Clean Investigation with a New Calorimetric Probe Concept — Thomas Kunstmann, Stefan Paulus, Infineon Technologies; Ing-Shin Chen, Horst Auer, Lin Feng, Richard Chism, Jeffrey F. Roeder, ATMI


  • Christopher Long, IBM Research
  • John Goodman, Entegris

Moving towards the 32 and 22 nm technology nodes, there is an ever increasing emphasis on contamination control and reduction which requires novel solutions and advanced measurement techniques. This session will discuss measurements for surface and airborne contamination as well as characterization of nanoparticles in process materials.


9.1 Opening Paper: Contamination Induced Risk Reduction through Improved Control Plan Implementation— P. Maillot, M. Le Gall, C. Martin, N. Pic, S. Iritz, STMicroelectronics

9.2 Increasing Yields with In-Tool Ionization— Arnold Steinman, MKS Ion Systems; Christopher W. Long, IBM Research

9.3 A New Surface Analysis Method for Semiconductor Manufacturing, Based on Surface-Potential Measurements— Ralf Schuetten, Matthias Kleber, Marko Jerenz, Bernd Zimmermann, Rainer Kaesmaier, Qimonda; Robert Newcomp, Joel Hickson, Noel Tamayo, QCEPT Technologies


Conference schedule subject to change.


Session 10: Advanced Metrology

Session 11: Yield Learning (sponsored by Synopsys)


  • José Estabil, Massachusetts Institute of Technology
  • Pascal Etman, Eindhoven University of Technology

The demand for high-quality reliable yield continues to drive advanced in metrology. This session offers new in-line metrology techniques to control end-of-line performance characteristics.

11:10 –12:55

10.1 Opening Paper: Impact of Intra-die Thermal Variation
on Accurate MOSFET Gate-length Measurement
— Ishtiaq Ahsan, Noah Zamdmer, Ronald Logan, Edward Nowak, Oleg Gluschenkov, IBM Microelectronics; Dieter Schroder, ASU

10.2 In-line Non-contact Measurement of Process Induced
In-Die Parametric Variability
— James Vickers, Bertrand Borot, Gary Steinbrueck, Gloria Johnson, Majid Babazadeh, Nader Pakdaman, tau-Metrix Inc.; Jean Galvier, ST-Crolles 2; Wim Doedel, EMMicroelectronic Marin

10.3 Novel In-line Inspection Method for Non-Visual Defects and Charging— K. Höppner, R. Manuwald, T. Fahr, E. Zschech, AMD Fab36 LLC & Co. KG; N. Tamayo, J. Hickson, B. Adrian, R. Newcomb, Qcept Technologies

10.4 Voltage Contrast Test Structure for Measurement
of Mask Misalignment
— Oliver D. Patterson, Stephen R. Fox, Kevin Wu, IBM Microelectronics



  • Gary Green, Synopsys
  • Hanno Melzner, Infineon

As new technologies continually challenge older methods, rapid yield learning has become essential in meeting today’s production challenges. In this session, we examine predictive parametric variation macros, diagnostics to pinpoint net failures, defect prediction using data mining and a 3D MEMS design approach to address yield issues before production.

11:10 –12:55

11.1 Opening Paper: Unified Fault Management Using L-BIST and Logic Bitmap— Douglas Kay, Lien Tran, Matthias Kamm, Cisco Systems; Jacob Orbon, Verigy

11.2 Towards Prediction of Latent Defects: Yield Mining Using Defect Characteristic Model and Clustering Algorithm (student paper)Melanie Po-Leen Ooi, Su-Lyn Lee, Wai Loon Chin, Ling Ying Goh, Ye Chow Kuang, Monash University; Chris Chan, Freescale

11.3 Advances on Yield Learning through Concurrent Evaluation of Design and Process Data in Light of ATPG Diagnostics— Davide Appello, Vincenzo Tancorre, STMicroelectronics; Christophe Suzor, Salvatore Talluto, Cy Hay, Sagar A. Kekare, Synopsys

11.4 3D Process Modeling—A Novel and Efficient Tool for MEMS Foundry Design Support— Gisbert Hölzer, Roy Knechtel, X-FAB Semiconductor Foundries; Gerold Schröpfer, Coventor Sarl


Conference schedule subject to change.


Session 12: Advanced Process Control

Session 13: Yield Methodologies


  • Ahmad Fathulla, Infineon
  • Stefan Radloff, Intel

Reducing process variation improves manufacturing efficiency and increases yield. This session presents papers on deposition, etch and laser annealing, demonstrating techniques for improved process control.


12.1 Opening Paper: Real Time APC: Solutions for Non Wafer Based Advanced Process Control and Predictive Maintenance— Leonid Yarin, Fadi Sakran, Numonyx

12.2 Application of a Run-to-Run Controller to a Vapor Phase
Epitaxy Process
— Cristina De Luca, Johannes Baumgartl, Infineon Austria; Enrico Maran, Alessandro Beghi, University of Padova

12.3 Optical Spectral Emission Endpoint Detection for Passivation Etch— Kenneth Yue Kok Hong, Chin Chye Seng, Chin Tiong Tay, James Se Kwang Leong, Boon Kiat Goh, Systems on Silicon Manufacturing

12.4 Application and Control of Laser Anneal at the 65 and 45 nm Node— R. Van Roijen, O. Gluchenkov, M. Hurley, IBM Systems & Technology Group; J. Willis, Ultratech


  • Daniel Maynard, IBM Microelectronics
  • Paul Werbaneth, Tegal

Semiconductor manufacturers are relentlessly searching for methodologies and techniques to improve the time to meaningful results. This session reviews several innovative approaches ranging from specific process sector analysis to a comprehensive short-flow program designed to boost productivity and end-of-line yield.


13.1 Opening Paper: Stackable Short Flow Characterization Vehicle to Reduce Test Chip Designs, Mask Cost and Engineering Wafers— Christopher Hess, Anand Inani, Amit Joag, Sa Zhao, Mark Spinelli, PDF Solutions; Binod Kumar, Long Nguyen, Chartered Semiconductor Manufacturing

13.2 Tool Sensitivity Analysis Using Neural Net Technique for Yield Improvement— P.K. Konkapaka, A. Pinto, P. Giotta, S. Bhattacharya, G. Verma, S. Murashov, M. Pathak, M. Menner, B.G. Smith, Qualcomm; S. Liu, S.T. Leu, W.S. Hung, C.J. Fu, J.C.H. Lin, K.C. Tsai, T.T. Chao, TSMC

13.3 Rule Induction for Identifying Multi Layer Tool Commonalities— Eric R. St. Pierre, Alexander Borisov, Igor Chikalov, Eugene Tuv, Intel

13.4 Novel SEM Based Imaging Using Secondary Electron Spectrometer for Enhanced Voltage Contrast and Bottom Layer Defect Review— Michal Avinun Kalish, Omer Sagy, Seong Moon Im, Applied Materials; ChangHwan Lee, Hynix Semiconductors

16:15–17:45 Panel Discussion: Growth Opportunities and Enabling Technologies for Semiconductor Manufacturers
Moderator: Tom Cheyney, Senior Contributing Editor, Fabtech and PV-Tech/Photovoltaic International



Keynote: Automated Precision Manufacturing in the Next Generation Factory
Thomas Sonderman,
vice president, Manufacturing Technology, The Foundry Company (AMD)

Session 14: The Best of ISSM



  • Jim Doran, Spansion
  • Lothar Pfitzner, Fraunhofer Institute
  • Thomas Sonderman, The Foundry Company (AMD)

The International Symposium on Semiconductor Manufacturing (ISSM) is an annual technical conference held alternating years in Japan and North America. This half-day session features “The Best of ISSM 2008 Japan.” Topics covered in this session include: Advanced Lithography; Environment, Safety and Health; Manufacturing Control and Execution: Process and Equipment Control: Process and Materials Optimization: and Yield Enhancement Methodology.



  • Going Green with On-Site Generated Fluorine: Sustainable Cleaning Agent for CVD Processes— Paul Stockman, Linde Electronics
  • Novel Single-Wafer, Single-Chamber Combined Dry and Wet System for Stripping and In-situ Cleaning of High-Dose Ion-Implanted Photoresists— Yi-jyung Kim, Semes Co. Ltd.
  • Enhancing Electrical Properties of Nickel Silicide by Using Spike Anneal as the Second Rapid Thermal Anneal— Takuya Futase, Renesas Technology
  • Focus and CD Control by Scatterometry Measurements for 65/45nm Node Devices— Toshihide Kawachie, Renesas Technology
  • Reducing Contamination of Particles Reflected in Turbo Molecular Pump— Hiroyuki Kobayashi, Hitachi
  • Interconnection Failure Caused by Bath Degradation in Copper Electroplating and its VM-FDC Using Mathmatical Model— Shin-ichi Imai, Panasonic
  • Defect Reduction in ArF Immersion Lithography, Using Particle Trap Wafers with CVD Thin Films— Yoshinori Matsui, NEC Electronics
  • In-line Inspection Impact on Cycle Time and Yield— Israel Tirkel, Ben-Gurion University

    12:00 Closing Remarks

Our sincere thanks and appreciation to ASMC and ISSM committee members,
whose combined expertise and efforts make ASMC 2009 a success.

ASMC 2009 Conference Co-Chairs
Walter Schoenleber
Applied Materials
Brett Williams
ON Semiconductor

ISSM International Committee Co-Chairs
Jim Doran
, Spansion
Thomas Sonderman
, The Foundry Company (AMD)

ASMC Steering and Technical Committee

Jeff Barnum, KLA-Tencor
Thomas Beeg, Qimonda
Jennifer Braggin, Entegris
Duane Boning, Massachusetts Institute of Technology
Thomas Carbone, Fairchild SemiconductorJohn Conway, Intel
Eric T. Eisenbraun, University at Albany

José Estabil, Massachusetts Institute of Technology
Pascal Etman, Eindhoven University of Technology
Ahmad Fathulla, Infineon Technologies Villach
Rainer Gehres, IBM Systems & Technology Group
John Goodman, Entegris
Nirmal Govind, Intel

Gary Green, Synopsys
Dave Gross, Advanced Micro Devices
Christopher Hess, PDF Solutions
Dick James, Chipworks
Franz-Josef Kahlen, University of Cape Town
Alfred Koenig, Applied Materials
Greg Klusewitz, Fairchild Semiconductodor
Scott Lantz, Intel
Holly Magoon, Nikon Precision
Daniel Maynard, IBM Microelectronics
Scott McClure, IBM Systems & Technology Group
Graham McFarlane, Linde Electronics
Mike McIntyre, Advanced Micro Devices
Winfried Meier, Nikon Precision Europe

Hanno Melzner, Infineon Technologies
William Miller, IBM Microelectronics
Kevin Nason, Fairchild Semiconductor
Kazunori Nemoto, Hitachi High Technologies
Oliver D. Patterson, IBM Microelectronics
Thomas Piliszczuk, KLA-Tencor France
Larry Pulvirent, Freescale Semiconductor
Stefan Radloff, Intel
Dieter Rathei, DR YIELD Software & Solutions
Ron Remke, International SEMATECH
Theresa Roeder, San Francisco State University
Leonard Rubin, Axcelis Technologies
Arthur Tay, National University of Singapore
Thuy Tran-Quinn, NXP Semiconductors
Helmuth Treichel, Xyratex
William Tyler, FSI International
Jacek Tyminski, Nikon Precision
Peter van der Meulen, BlueShift Technologies
Paul Werbaneth, Tegal
Kenny Ye, Hitachi High Technologies America


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Full Conference (Non-member) euro625/person

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Day 3 Only (13 May) euro310/person

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Student euro 50/person

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ASMC Discount

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Hotel Information

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Budapester Str. 25, 10787 Berlin
T: +49.30.2696.0 F: +49.30.2696.1000

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