Materials, ihLithography Challenges at 45 nm and 32 nm to be Discussed at SEMICON West
One of the biggest manufacturing challenges in the industry today is scaling down to 45 nm and beyond. Current technology relies on oxynitride gate dielectrics, but to meet the International Roadmap for Semiconductors (ITRS) requirements for gate performance, it is likely that different materials will have to be identified, qualified and implemented in fabs—and the timetable for this activity is rather short. With recent announcements by several leading companies of advanced research and testing of materials, such as hafnium silicon oxynitride (HfSiON), a feasible new dielectric material may now be ready to move the industry forward.
These and other enabling technologies will be on display at this year’s SEMICON® West Device Scaling TechXPOT—the show floor conference sessions—including the readiness of the industry to adopt high-k metal gates at the 45 nm node, and lithography, metrology challenges at the 32 nm node.
On Tuesday, July 17 , at 10:30am, the Device Scaling session will start off with two interesting presentations. First, Raj Jammy, an IBM (East Fishkill, New York) assignee to SEMATECH (Austin, Texas), will discuss the current state of high-k metal gates, including an analysis of the industry’s capability to manufacture these gates and the promise of future scaling with these structures. On May 23, IBM said it would collaborate with a larger group of chip makers on 32 nm semiconductor production technologies using high-k, metal gate technology. That group includes Chartered Semiconductor Manufacturing Ltd., Freescale Semiconductor Inc., Infineon Technologies AG and Samsung Electronics Co. Jammy, director of SEMATECH’s Front End Processes division, will present his point of view on specific manufacturing issues, including the likelihood of using atomic layer deposition (ALD).
Taking the stage at 10:50am is Reza Arghavani, fellow, Applied Materials (Santa Clara, California). Arghavani will take the manufacturability topic of high-k metal gates to a detailed level as he discusses the industry’s response to this manufacturing challenge. Arghavani is expected to describe the processes being used in DRAM manufacturing today (including some actual examples of high-k gate integration) and the steps for adoption across the industry in the near-term.
TI also plans to use high-k for gate-stack applications, as traditional silicon oxide materials are running out of gas. EETimes reports that TI will leverage a chemical vapor deposition (CVD) process to deposit hafnium silicon oxide (HfSiO), followed by a reaction with a downstream nitrogen plasma process to form HfSiON or hafnium silicon oxynitride.
On Wednesday, July 18 from 3:00pm to 5:00pm, Materials and Equipment Challenges for 32 nm Development will be the topic of discussion for speakers from IBM, Intel, AMD, and others. Michael Lercel, director of the lithography division of SEMATECH and assignee from IBM Microelectronics, will discuss EUV lithography, and Mark Buehler, Ph.D. from Intel will address CMP Challenges at 32 nm. Faced with possible delays for extreme ultraviolet (EUV) lithography, Intel Corp. recently disclosed that it is hedging its bets by developing a design-for-manufacturing (DFM) technology that could extend optical scanners to the 22-nm node. Two companies—ASML Holding NV and Nikon Corp.—are or will shortly deliver EUV tools, but those systems are still in the early prototype stages.