Program online registration until 8 / 31

3D IC Technology Forum Thursday, September 9th, 2010 08:30 –17:00 Room 201ABC, 2F, Taipei International Convention Center, Taipei Event Fee : Free (Pre-registration is required)

Theme : The Coming-of-age of 2.5D & 3D ICs

Forum Chair :
Dr. Ho-Ming Tong, Chairman, SEMI Taiwan PKG&TEST Committee / GM & CTO, ASE Group

Co-chairs :
Dr. Shen-Li Fu, Vice Chairman of SEMI Taiwan PKG&TEST Committee / President, I-Shou University
Dr. YJ Chan, Vice Chairman of SEMI Taiwan PKG&TEST Committee / VP & EOL General Director, ITRI
Dr. Sitaram Arkalgud, Director of 3D Interconnect, SEMATECH

Outline :
Consumer devices will drive 10-1000x computations and 10x data rate in this decade to deliver compelling user experiences. As the end of planar CMOS transistor scaling is near, 3D IC holds great promises to bridge the gaps between SoC and future system requirements. Despite great strides made in the recent past, 3D IC still presents significant challenges in manufacturing, integration, infrastructure and business model. Driven by handheld and PC applications, these challenges will likely be overcome in the next few years.

Before 3D IC is commercialized on a large scale, 2.5D IC based on silicon interposer has attracted much attention as it paves the road for 2D IC to migrate to 3D IC using the existing infrastructure. In this symposium, leaders covering the entire eco-system from the perspectives of whole industry will share their experiences in 2.5D and 3D ICs with a special emphasis on emerging business models, manufacturing readiness, roadmap, as well as inter-dependencies with others in the eco-system.

Agenda :

08:30 – 09:00	Registration
09:00 – 09:10	Welcome Remarks 1. Executive from SEMI 2. Dr. Ho-Ming Tong, General Manager & Chief R&D Officer, ASE Group 3. Mr. Daniel Armbrust, President & CEO, SEMATECH
09:10 – 09:50	Opening Speech - Industry Overview Dr. Ho-Ming Tong, General Manager & Chief R&D Officer, ASE Group
09:50 – 10:30	Market Perspective Mr. Jean-Christophe Eloy, President and CEO, Yole Développement
10:30 – 11:10	3D IC Technology from End User Point of View Mr. Kauppi Kujala, Senior Technology Manager, PWB & Packaging Solutions, Technology, Devices R&D, Nokia Corporation
11:10 – 11:50	The Coming of Age of 2.5D and 3D IC’s : Interface Standardization for 3D Product Realization Mr. Nicholas Yu, Vice President, Engineering, Qualcomm
11:50 – 12:30	IC Foundry & Fab Perspective Mr. Shan-Chieh Chien, Vice President of ATD, UMC
12:30 – 14:00	Lunch Break
13:30 – 14:00	Afternoon Registration
14:00 – 14:30	The coming-of-age of 2.5D & 3D ICs Mr. Carl Chen, VP, Manufacturing Group, SPIL
14:30 – 15:00	Semiconductor Testing in the Third Dimension Dr. Erik H. Volkerink, CTO, Verigy Ltd.
15:00 – 15:30	3D IC TSV Processing Mr. Sesh Ramaswami, Sr. Director, Silicon Systems Group, Strategic and 3D IC TSV Program, Applied Materials
15:30 – 16:00	Progress Update of Thin Wafer Handling Dr. Wei-Chung Lo, Director, Package Technology Div., EOL, ITRI
16:00 – 16:30	3D IC Integration with TSV – Current Progress and Future Outlook Dr. Gao Shan, Program Manager, 3D TSV Program, IME
16:30 – 17:00	Supply Chain Readiness from Institute Perspective Dr. Sitaram Arkalgud, Director of 3D Interconnects, SEMATECH
17:00	Adjournment

● Programs are subject to change without prior notice.
● All presentations will be conducted in English.

Chair Introduction:

Dr. Ho-Ming Tong, Chairman, SEMI Taiwan PKG&TEST Committee / GM & CTO, ASE Group ● General Manager of Group R&D, ASE Group ● IEEE Fellow for leadership in leading-edge integrated circuits technology ● Electronics Manufacturing Technology Award from IEEE Components ● 2005 the highest recognition for technical leaders ● 2010 the Outstanding Research Award of Pan Wen Yuan Foundation ● He has authored/co-authored 112 patents, 100+ technical publications, as well as 2 books and 2 special journal issues on electronic packaging《Top》

Co-Chairs Introduction:

	Dr. Shen-Li Fu, Vice Chairman of SEMI Taiwan PKG&TEST Committee / President, I-Shou University ● Educational Background −National Chen-Kung University Ph.D. degree; 1977 −Majored in Electrical Engineering M.S. degree; 1972 −Majored in Electrical Engineering B.S. degree; 1969 ● Executive Working Experience −I-Shou University President; 1998 - now −Kaohsiung Polytechnic Institute President; 1990 - 1998 −National Chen-Kung University Dean of the Student Affairs;1987 - 1989 ● Honors & Awards −IEEE-CPMT, 2007 President Recognition Award −IMAPS, 2006 President Recognition Award −IMAPSS, 2003 Fellow −National Science Counsel, 1990 Outstanding Research Award −International Invention Expo, 1986 Gold-Plate Award −Ministry of Education, 1983 Outstanding Research Award −Patents of several kinds《Top》
	Dr. YJ Chan, Vice Chairman of SEMI Taiwan PKG&TEST Committee / VP & EOL General Director, ITRI ● General Director, EOL/ITRI ● Professor, National Central University ● Professor, National Chiao Tung University ● Chairman of EE Dept., National Central University ● Received Science Paper Award of Far Eastern Y. Z. Hsu Science and Technology Memorial Foundation in 2006 ● Owned 18 patents《Top》
	Dr. Sitaram Arkalgud, Director of 3D Interconnect, SEMATECH Dr. Sitaram R. Arkalgud is Director of SEMATECH’s Interconnect Division, which develops new interconnect technologies for tomorrow’s advanced computer chips. The current activities are focused on delivering manufacturable process technologies for 3D interconnects using Through Silicon Vias. Previously, the Division worked on porous low k dielectric and Cu metallization technologies for VLSI. Arkalgud has more than 19 years of R&D and manufacturing experience in areas within the chip industry. He is the author of over 25 publications and holds 14 U.S. patents. Prior to joining SEMATECH, Arkalgud served as Infineon’s Director and Project Manager of the MRAM Development Alliance between Infineon and IBM where he led a global, multinational team in developing and productizing magnetic RAM (MRAM).He also worked as a technology officer and product manager for Infineon. Earlier, Arkalgud functioned as a senior principal staff engineer/scientist at Motorola, Inc., working in logic and advanced memory projects. Arkalgud holds a doctorate and master’s degree in materials engineering from Rensselaer Polytechnic Institute in Troy, NY, and a bachelor’s degree in metallurgical engineering from Karnataka Regional Engineering College, Suratkal, India. 《Top》

Speaker Introduction:

	Dr. Ho-Ming Tong, Chairman, SEMI Taiwan PKG&TEST Committee / GM & CTO, ASE Group ● General Manager of Group R&D, ASE Group ● IEEE Fellow for leadership in leading-edge integrated circuits technology ● Electronics Manufacturing Technology Award from IEEE Components ● 2005 the highest recognition for technical leaders ● 2010 the Outstanding Research Award of Pan Wen Yuan Foundation ● He has authored/co-authored 112 patents, 100+ technical publications, as well as 2 books and 2 special journal issues on electronic packaging《Top》
	Mr. Jean-Christophe Eloy, President and CEO, Yole Développement ● JC Eloy has created YOLE Développement in 1998 and is managing Yole Développement in term of international development and strategic orientations of the company. He is directly in charge of the Mems and 3D IC activities at Yole Développement ●JC Eloy and the 20 analysts of YOLE Développement are working directly with the key players of the industry from equipment and materials suppliers to device manufacturers and system integrators. ●Jean-Christophe Eloy has been 6 years manager of the marketing department of CEA/LETI (France), applied R&D organization involved in the semiconductor, Mems and instrumentation fields (1300 researchers). He then created the semiconductor practice at Ernst & Young in Europe and worked as senior manager in charge of the development of European activities. ●Jean-Christophe Eloy is involved since 1991 in the Mems and semiconductor areas. ●JC Eloy is Engineer from INPG/ENSERG (semiconductor and telecommunications) and has a MBA from EM Lyon. 《Top》
	Mr. Kauppi Kujala, Senior Technology Manager, PWB & Packaging Solutions, Technology, Devices R&D, Nokia Corporation ●Nokia, R&D 1999 – Present −PWB & IC Packaging Technology Management −Technology Manager, Engineering Manager, Team Leader, Project Manager, R&D Engineer ●VTI Technology 1996 – 99 −MEMS Technology Company −Project Engineer – Product development ●M.Sc. degree in Materials Science from Helsinki University of Technology 1996 ●Invited Speaker e.g. in −SEMICON Europe Oct 2008 −RTI Conference on 3D IC Packaging Oct 2007 −SEMICON Japan Dec 2006《Top》
	Mr. Nicholas Yu, Vice President, Engineering, Qualcomm Nick Yu is a Vice President of Engineering at Qualcomm’s CDMA Technologies Division. He is currently responsible for setting Qualcomm’s semiconductor technology roadmaps including wafer fab process node, backend interconnect and packaging technologies. He manages engineering teams that are involved with our supply chain partners on execution of the technology roadmaps for Qualcomm’s chipset products. Nick has over 17 years of experience with Qualcomm on low power wireless chipset and SoC development, including managing chipset design, advanced semiconductor technology, deep submicron circuit design and methodology development, advanced semiconductor R&D and packaging development. He is one of the architects of, and has participated in the definition and development of, many Qualcomm chipset products. 《Top》
	Mr. Carl Chen, VP, Manufacturing Group, SPIL ●Education: −Master of Science Warwick University, UK ●Experience: −Advanced packaging R&D −Customer service in SPIL-USA《Top》
	Dr. Erik H. Volkerink, CTO, Verigy Ltd. ● Senior Director of Technology and Chief Scientist, Verigy 2008-2010 ● Chief Scientist, Verigy, 2007-2008 ● General Chair and Founder of ATEVision 2020 ● Program Chair International Test Conference (ITC2010) ● Cost of Test Section Lead of the International Technology Roadmap for Semiconductors (ITRS) ● Consulting Assistant Professor, Electrical Engineering Department, Stanford University, 2004-2010 ● PhD Electrical Engineering, Stanford University ● MBA Wharton School of Business, Pennsylvania《Top》
	Dr. Wei-Chung Lo, Director of package technology division, ITRI ● Director of package technology division, ITRI ● M.S. degree and Ph.D. in Chemistry from National Taiwan University, Taiwan ● Wharton school AMP 2010, US ● Executive Secretary of 3DIC consortium(Ad-STAC) ● Program Committee Chair of International Microsystems, Packaging, Assembly and Circuits Conference(IMPACT conference 2009) ● Chair of Advanced Microsystem and Packaging Alliance, the largest package alliance in Taiwan (AMPA) ● holds 8 patents and has published over 20 papers《Top》
	Dr. Gao Shan, Program Manager, 3D TSV Program, IME ●Technical Manager, Microsystems, Modules & Components (MMC) laboratory, Program Manager, 3D TSV Program, Institute of Microelectronics, Singapore ●Senior Manager, Packaging Department, Research & Development Center, Samsung, Korea ●Senior Development Engineer, Research & Development Center, C.D.P. Corporation, Germany ●Ph.D, Department of Material Science and Mechanics of Materials, School of Mechanical Engineering, Technical University of Munich, Germany《Top》
	Dr. Sitaram Arkalgud, Director of 3D Interconnects, SEMATECH Dr. Sitaram R. Arkalgud is Director of SEMATECH’s Interconnect Division, which develops new interconnect technologies for tomorrow’s advanced computer chips. The current activities are focused on delivering manufacturable process technologies for 3D interconnects using Through Silicon Vias. Previously, the Division worked on porous low k dielectric and Cu metallization technologies for VLSI. Arkalgud has more than 19 years of R&D and manufacturing experience in areas within the chip industry. He is the author of over 25 publications and holds 14 U.S. patents. Prior to joining SEMATECH, Arkalgud served as Infineon’s Director and Project Manager of the MRAM Development Alliance between Infineon and IBM where he led a global, multinational team in developing and productizing magnetic RAM (MRAM).He also worked as a technology officer and product manager for Infineon. Earlier, Arkalgud functioned as a senior principal staff engineer/scientist at Motorola, Inc., working in logic and advanced memory projects. Arkalgud holds a doctorate and master’s degree in materials engineering from Rensselaer Polytechnic Institute in Troy, NY, and a bachelor’s degree in metallurgical engineering from Karnataka Regional Engineering College, Suratkal, India. 《Top》

Presentation Abstract:

3D IC Technology from End User Point of View Mr. Kauppi Kujala, Senior Technology Manager, PWB & Packaging Solutions, Technology, Devices R&D, Nokia Corporation ●3D-IC outlook & early adaptation ●System requirement ●Standardization activities ●3D packaging roadmap ●Expectations & Challenges ●Summary《Top》

The Coming of Age of 2.5D and 3D IC’s : Interface Standardization for 3D Product Realization Mr. Nicholas Yu, Vice President, Engineering, Qualcomm 3D Through-Si-Via based integration technology has a lot of momentum in the industry, and there is general agreement that the industry needs a number of new technical and interfacing standards. Qualcomm has explored and confirmed the value proposition of this technology, and for the last few years has been an active leader in the R&D and productization efforts in the fabless industry. We believe in the next 3 to 5 years, the value proposition associated with 3D Through-Si-Stacking (TSS) technologies will be commercialized with products that use heterogeneous integration of dies from multiple sources. We have also identified many technical and business gaps caused by the lack of easy interoperability among the supply chain players. Although there is a lot of will in the industry, there is no clear way of deploying standards, interfacing design models, and roles and responsibilities of the supply chain players. These gaps are illustrated in this talk using a specific example of a heterogeneous integration flow. We will present a proposal for required standards, along with ownerships and roles and responsibilities amongst existing standards bodies. 《Top》

The coming-of-age of 2.5D & 3D ICs Mr. Carl Chen, Vice President, Manufacturing Group, SPIL In this moment, this industry is frustrated with following Moore’s law to miniaturize microelectronics, due to huge investment in RD and facilities. It’s helpful, 3D (More than Moore) is a good solution to integrate different function chips in same package, experts define a true 3D package as one that stacks various chips vertically and then connects them by using TSV, to shorten the interconnections between the chips, reduce size and up bandwidth. But, the processor giant Intel is still in search of the right chip application for 3D, another giant IBM said, a production-worthy device is not expected until 2012, IBM also mentioned, there are five challenges for 3D devices, including lack of EDA design tools, complexity of designs, integration of assembly and test, heterogeneous system integration, and standards, so far, SEMI is doing something on the road, and some chip makers are shipping CMOS image sensors mainly, MEMS, and some power amplifiers already. But, the price of doing 3D is still very high, according to EETimes report. 2.5D is the bridge from 2D to 3D, this is a temporary solution to overcome 3D challenges and difficulties in this moment. In this presentation will introduce 3D and 2.5D solutions, the interposer and vertical integration technology (VIT) in SPIL, VIT, it’s new and feasible technology, it’s valuable for flash memory and different dies stacking. 《Top》

Semiconductor Testing in the Third Dimension Dr. Erik H. Volkerink, CTO, Verigy Ltd. Moore’s law continues to move forward with denser, large, faster, and highly heterogeneous devices coming our way, in part enabled through 3D integration. These issues, when added to ever increasing test complexity, cost-of-test, and time-to-market pressures, pose a significant challenge to the ATE industry. In this presentation, we will give an overview of the challenges as well as required areas for innovation to make sure we continue to scale the cost of test with Moore’s Law. 《Top》

Progress Update of Thin Wafer Handling Wei-Chung Lo, Director of package technology division, ITRI 3D IC is expected as a key enabler for performance and market growth of semiconductor industry. For Foundry, packages, or equipment Manufacturers, there has been much progress to demonstrate the technology approach and some key challenges are found as well. Thin wafer handling is one of them and attracts much more intention to all players. Currently, different thinning technologies are proposed by companies to support the thin wafer either Bernoulli handling system or thin wafer with carrier. Future possible thin wafer handling integrated technology platforms, new consolidation and new manufacturing service are proposed and discussed in this speech《Top》

3D IC Integration with TSV – Current Progress and Future Outlook Dr. Gao Shan, Program Manager, 3D TSV Program, IME Over the past few decades, semiconductor chips have kept on increasing their performances while decreasing the sizes. More devices, such as digital/analog device, optoelectronics, and MEMS etc, need to be integrated into a single chip. 3D integrated circuits (3D IC) offer significant performance benefits at that with minimized interconnect length by 3D routing in designs the 3D IC can operate at higher clock rates and consume less power. In addition 3D IC will significantly simplify chip to chip communications and the data transfer among the processing elements, resulting in faster signal/data throughput so that high frequency and high transfer rate can be achieved. The interconnection between stacked chips in 3D IC has been realized by through silicon via (TSV). This talk will summarize the recent advancements of 3D IC integration with TSV in design, process and test technologies. Various challenges which may significantly affect the performance and reliability of 3D IC and its further applications will be addressed in this talk. 《Top》

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